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TP-LINK TL-MR3020 v1
Availability: now

FCC approval date: 21 February 2012
(Est.) release date: 13 January 2012
UPC: 845973051709 (UPC DB, On eBay)
EAN: 6935364051709 (UPC DB, On eBay)
Country of manuf.: China

Amazon image

B00634PLTW (Flag of the United States.svg, On Amazon, On CCC)Expression error: Unrecognized word "span".

Type: mobile router


Power: 5 VDC, 1 A
Connector type: USB Female Mini-B

CPU1: Atheros AR9331
FLA1: 4 MiB
4,194,304 B
32,768 Kib
4,096 KiB
32 Mib
0.00391 GiB
(Spansion FL032PIF)
RAM1: 32 MiB
33,554,432 B
262,144 Kib
32,768 KiB
256 Mib
0.0313 GiB
(Winbond W9425G6JH-6)

Expansion IFs: USB 2.0
USB ports: 1

WI1 chip1: Atheros AR9331
WI1 802dot11 protocols: bgn
WI1 MIMO config: 1x1:1
WI1 antenna connector: none

ETH chip1: Atheros AR9331
LAN speed: 10/100
LAN ports: 1


Third party firmware supported: OpenWrt, libreCMC

Flags: 3G capable

802dot11 OUI: none specified

For a list of all currently documented Atheros chipsets with specifications, see Atheros.

Portable 3G Wireless N Router

Product page

Notes on JTAG[edit]

The EJTAG interface AR9331 is different from the ones on most chips:

  • First of all, the Jtag pins are multiplexed with GPIOs, GPIO11 must be pull high to bootstrap the debug interface.
Pressing the SW2 switch while powering on the unit should take care of this as it is connected to GPIO11.
  • The second problem is that U-Boot will disable EJTAG, even if it was enabled by pulling GPIO11 high during power up.
To workaround this, a jumper can be added between the CS pin on the flash and CPU.
  • And last problem is that TP-Link does not provide test points, pads or pins for the Jtag interface.


This sequence will be needed to initiate PLL and RAM: