Atheros.For a list of all currently documented Atheros chipsets with specifications, see
Portable 3G Wireless N Router
Notes on JTAG
The EJTAG interface AR9331 is different from the ones on most chips:
- First of all, the Jtag pins are multiplexed with GPIOs, GPIO11 must be pull high to bootstrap the debug interface.
- Pressing the SW2 switch while powering on the unit should take care of this as it is connected to GPIO11.
- The second problem is that U-Boot will disable EJTAG, even if it was enabled by pulling GPIO11 high during power up.
- To workaround this, a jumper can be added between the CS pin on the flash and CPU.
- And last problem is that TP-Link does not provide test points, pads or pins for the Jtag interface.
This sequence will be needed to initiate PLL and RAM:
|PLL / RAM|
#pll initialization mww 0xb8050008 0x00018004 mww 0xb8050004 0x00000352 mww 0xb8050000 0x40818000 mww 0xb8050010 0x001003e8 mww 0xb8050000 0x00818000 mww 0xb8050008 0x00008000 sleep 1 # Setup DDR1 config and flash mapping mww 0xb8000000 0x7fbc8cd0 mww 0xb8000004 0x9dd0e6a8 mww 0xb8000010 0x8 mww 0xb8000008 0x133 mww 0xb8000010 0x1 mww 0xb800000c 0x2 mww 0xb8000010 0x2 mww 0xb8000010 0x8 mww 0xb8000008 0x33 mww 0xb8000010 0x1 mww 0xb8000014 0x4186 mww 0xb800001c 0x8 mww 0xb8000020 0x9 mww 0xb8000018 0xff #UART mww 0xb8020004 0x4388 mww 0xb8020008 0xc2000 #GPIO mww 0xb8040028 0x48002