See 'WikiDevi' @ the Internet Archive (MW XML, Files, Images)
upgraded MW to 1.30 - maybe things are slightly less broken
MIPS 74Kc / MIPS 74Kf
- Processor Identification: 00019740 (Processor ID: 0x97; Rev: 2.0.0)
The MIPS32 74K is based on a superscalar asymmetric dual-issue pipeline microarchitecture
- with out-of-order (OoO) instruction dispatch and completion.
The implementation features a 15-stage pipeline to achieve high synthesizable frequencies, and
- supports up to 4 instructions fetched per cycle, plus up to 4 instructions issued per cycle.
The 74Kc/f incorporates the MIPS DSP Module Rev2 for enhanced signal processing capabilities.
The 74Kc/f includes an OCP Bus Interface Unit and connection to an optional L2 cache controller
- and delivers a performance of 1.93 DMIPS/MHz and 3.48 Coremarks/MHz.
The core also includes an IEEE754 compliant Floating Point Unit, supporting both single
- and double precision datatypes.
The 74K family has two members: the MIPS32 74Kc core and the MIPS32 74Kf core:
- MIPS 74Kc 32-bit RISC core is optimized for high-performance applications.
- MIPS 74Kf core adds an IEEE-754 compliant floating point unit.
The core implements the MIPS32 Release 2 Instruction Set Architecture (ISA).
- It also implements the following Application-Specific Extensions (ASEs):
- The MIPS DSP Application-Specific Extension (ASE) is optimized for signal-processing applications.
- The MIPS16e Application-Specific Extension (ASE) is optimized for code compression.
|Release Identifier|| PRId [Revision] /
|1_0_*||1.0.0 / 0x20||Early-access release of 74K family RTL.||January 31, 2007|
|2_0_0*||2.0.0 / 0x40||First generally-available release of 74K family core.||May 11, 2007|
|2_1_0*||2.1.0 / 0x44||Can wait with interrupts disabled.||October 31, 2007|